The present invention relates to electrostatic discharge protection of semiconductor devices, and more particularly to an active ESD clamp circuit for core circuitry protection.
With the rapid development of semiconductor manufacturing technology, small-sized transistors having a thin gate oxide layer and a thin dielectric layer can easily be damaged due to electrostatic discharge. Thus, a secondary ESD protection of the core circuitry is indispensable for sub-micron modules and structures.
Integrated circuits with large feature sizes have a large number of buffer transistors configured to share an ESD current so that the amount of the ESD current flowing through each buffer transistor is manageable, so that no damage occurs. Integrated circuits with small-feature sizes do not have a sufficient number of buffer transistors to share the ESD current so that the transistors can easily be damaged. Small feature-sized (e.g., submicron) integrated circuits fully depend on the internal ESD protection circuitry to absorb the ESD current, even a relatively small ESD current can cause significant damage to the submicron circuitry. Generally, internal circuit transistors that connect to Vcc power supply and Vss ground supply may directly dissipate an ESD current because the large number of transistors can reduce the current surge. However, for small supply domains, tiny devices may fail even with an internal ESD clamp device, the reason is that the time constant for trigger an ESD clamp gate is not sufficient to keep the ESD clamp device remain turned on. Conventional internal ESD protection circuits do not have sufficient long turn-on time to fully discharge the ESD current to protect the core circuitry. Thus, increasing the turn-on time of the ESD protection circuitry is required.
In general, an ESD protection circuit is coupled between the power supply and ground supply to protect the core circuitry. An ESD protection circuit is an active device that drives the gate of an n-channel clamp transistor. The clamp transistor shunts an ESD current from the power supply to ground when its gate is driven high during an ESD event. The ESD protection circuit may include a voltage divider that generates a sense voltage to drive a first inverter. The initial input terminal ESD voltage is much lower than the threshold of a first inverter. When the ESD voltage reaches its peak value, the switching output of ESD voltage is higher than the threshold of the first inverter, whose output takes on a logic high level. The logic high level of the output of the first transistor travels through a series of inverters to turn the output of the last inverter connected to the gate of the N-channel active clamp transistor to the logic high level to turn on the N-channel clamp transistor. The output of the last extending transistor is connected between a gate of an n-MOS transistor and the input of the last inverter. This structure extends the turn-on time of the N-channel clamp transistor to increase the discharge duration of the ESD current, thereby increasing the ESD protection of the core circuitry.
Conventional ESD clamp circuits may utilize a resistor-capacitor (RC) circuit to detect the occurrence of an ESD event. The extension of the discharge time can be increased by increasing the value of the resistor and/or capacitor. However, increasing the value of the resistor and/or capacitor also increases the silicon area. Furthermore, a large value of resistor and/or capacitor may lead to a large leakage current flowing through the clamp transistor when a voltage power is on. Thus, conventional ESD protection circuits have many disadvantages and limitations that add greatly to the difficulty and cost of manufacture.